Within any given integrated circuit technology and due to a number of factors, signal processing techniques have been limited to signal frequencies and data rates at substantially less than state-of-the-art circuit speeds. As but one example of how this has limited the electronic arts, the transmission rate of a high-speed communication channel between two integrated circuits having no external components has been limited by the ability to reliably extract receive signals from the inherent ringing induced by the channel interconnect. Above certain speeds, and without the benefit of external components, it has been presumed that reliable transmission was not possible, as there has been no ability to do time-domain wave shaping in real-time.
Classical analog time/frequency-domain filter-techniques have been precluded by the lack of predictable time constants or the need for undesirable large or discrete components, especially bulky inductors. Switched-capacitor filter implementations require expensive (power, area) and relatively frequency limited operational amplifiers and relatively large precision-area-ratio capacitors.
Digital signal processing (DSP) techniques, such as the finite impulse response (FIR) filter, only require basic DSP building blocks including delay elements, multipliers, and accumulators. All these functions are easily implemented with complete accuracy in the digital domain. The FIR filter is especially suited for adaptive filtering techniques as taught in xe2x80x9cAdaptive Filtersxe2x80x94A Review of Techniques,xe2x80x9d by Hughes, et al., appearing as chapter 3 in xe2x80x9cDigital Signal Processing in Telecommunications,xe2x80x9d edited by F. A. Westall, et al., published in 1993 by Chapman and Hall, London. Unfortunately, the basic DSP building blocks are expensive to implement as digital logic or they require software implementations that function at a fraction of the channel speed.
For general computer applications, there are a large number of channels operating at roughly the same rate. Thus expensive solutions, even if possible for a single pair of channel transceivers, are not practical options, as the large number of simultaneously operating channels prohibitively multiplies their expense.
Signal processing techniques may be applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by using hybrid analog and digital circuit techniques to carry out the signal flow graph of a canonical FIR filter algorithm. The FIR filter makes use of a tapped delay line, multipliers, multiplier tap coefficients, and an accumulator. As one example of how this technique benefits the electronic arts, the transmission rate of a high-speed communication channel between two integrated circuits having no external components can be substantially extended over prior art efforts. This is due to the ability to reliably extract receive signals from the inherent ringing induced by the channel interconnect.
More specifically, the circuit techniques include the following. A plurality of delay signals (delayed versions of the signal to be filtered) are generated. These delay signals are the analogue of the tap signals of the tapped delay line of the FIR filter model. Each binary (0, 1) tap signal is mapped into a differential switching logic signal pair (+1, xe2x88x921).
A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The differential delay signals are connected to the inputs of respective ones of the differential pair stages. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. In particular, a logical one maps to an analog +1, which turns on the associated differential-pair input device and routes the entirety of the tail current through the xe2x80x9cturned-onxe2x80x9d input device and to the associated load circuit for summation with current contributions from other xe2x80x9cturned-onxe2x80x9d input devices. A logical zero maps to an analog xe2x88x921, which turns off the associated differential-pair input device. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices. This current summation is the analogue of the FIR accumulator. Because the tap coefficient currents are readily programmable, the filter may be adaptive.
The present invention finds particular application in the design of the channel interface circuitry for contemporary high-speed multiprocessor systems, such as those disclosed in the applications previously incorporated by reference above.